rev. 3.3 - 4/09/98 1 1 2 3 4 5 6 7 8 9 10 11 12 functional block diagram features n high-speed access times com?: 10, 12 and 15 ns ind?: 12 and 15 ns n low power operation (typical) - pdm41024sa active: 450 mw standby: 50 mw - pdm41024la active: 400 mw standby: 25mw n single +5v ( 10%) power supply n ttl-compatible inputs and outputs n packages plastic soj (300 mil) - tso plastic soj (400 mil) - so plastic tsop (i)- t description the pdm41024 is a high-performance cmos static ram organized as 131,072 x 8 bits. writing is accomplished when the write enable (we ) and the chip enable (ce 1) inputs are both low and ce2 is high. reading is accomplished when we and ce2 remain high and ce1 and oe are both low. the pdm41024 operates from a single +5v power supply and all the inputs and outputs are fully ttl- compatible. the pdm41024 comes in two versions: the standard power version (sa) and the low power version (la). the two versions are functionally the same and differ only in their power consumption. the pdm41024 is available in a 32-pin plastic tsop (i), and a 300-mil and 400-mil plastic soj. a a 0 16 i/o i/o 0 7 ce1 we addresses decoder memory matrix input data control column i/o oe ce2 control pdm41024 1 megabit static ram 128k x 8-bit
pdm41024 2 4/09/98 - rev. 3.3 pin con?uration soj a11 a9 a8 a13 we ce2 a15 vcc nc a16 a14 a12 a7 a6 a5 a4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 oe a10 ce1 i/o7 i/o6 i/o5 i/o4 i/o3 vss i/o2 i/o1 i/o0 a0 a1 a2 a3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 15 16 17 18 19 20 21 22 23 24 nc
a16
a14
a12
a7
a6
a5
a4
a3
a2
a1
a0
i/o0
i/o1
i/o2
vss vcc
a15
ce2
we
a13
a8
a9
a11
oe
a10
ce1
i/o7
i/o6
i/o5
i/o4
i/o3 13 14 25 26 27 28 29 30 31 32 truth table (1) note: 1. h = v ih , l = v il , x = don? care oe we ce1 ce2 i/o mode x x h x hi-z standby x x x l hi-z standby lhlhd out read xllhd in write h h l h hi-z output disable pin description name description a16-a0 address inputs i/o7-i/o0 data inputs/outputs oe output enable input we write enable input ce1 , ce2 chip enable inputs nc no connect v cc power (+5v) v ss ground tsop (i) absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. exposure to absolute maximum rating con- ditions for extended periods may affect reliability. 2. appropriate thermal calculations should be performed in all cases and speci?ally for those where the chosen package has a large thermal resistance (e.g., tsop). the cal- culation should be of the form : t j = t a + p * q ja where t a is the ambient temperature, p is average operating power and q ja the thermal resistance of the package. for this product, use the following q ja values: soj: 72 o c/w tsop: 95 o c/w symbol rating com l. ind. unit v term terminal voltage with respect to v ss ?.5 to +7.0 ?.5 to +7.0 v t bias temperature under bias ?5 to +125 ?5 to +135 c t stg storage temperature ?5 to +125 ?5 to +150 c p t power dissipation 1.0 1.0 w i out dc output current 50 50 ma t j maximum junction temperature (2) 125 145 c
pdm41024 rev. 3.3 - 4/09/98 3 1 2 3 4 5 6 7 8 9 10 11 12 recommended dc operating condition dc electrical characteristics (v cc = 5.0v 10%) note: 1. v il (min) = ?.0v for pulse width less than 20 ns power supply characteristics shaded areas = preliminary data notes: all values are maximum guaranteed values. v lc 0.2v, v hc 3 v cc ?0.2v symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v v ss supply voltage 0 0 0 v industrial ambient temperature ?0 25 85 c commercial ambient temperature 0 25 70 c pdm41024sa pdm41024la symbol parameter test conditions min. max. min. max. unit i li input leakage current v cc = max., v in = v ss to v cc com?/ ind. 55 11 m a i lo output leakage current v cc = max., ce1 = v ih and ce2 = v il, v out = v ss to v cc com?/ ind. 55 11 m a v il input low voltage ?.5 (1) 0.8 ?.5 (1) 0.8 v v ih input high voltage 2.2 6.0 2.2 6.0 v v ol output low voltage i ol = 8 ma, v cc = min. i ol = 10 ma, v cc = min. 0.4 0.5 0.4 0.5 v v v oh output high voltage i oh = ? ma, v cc = min. 2.4 2.4 v -10 -12 -15 symbol parameter power com l. com l. ind. com l. ind. i cc operating current ce1 = v il and ce2 = v ih sa 250 230 240 185 195 f = f max = 1/t rc v cc = max. i out = 0 ma la 230 210 220 165 175 i sb standby current ce 1 = v ih and ce2 = v il sa 80 70 70 55 55 f = f max = 1/t rc v cc = max. la 75 65 65 50 50 i sb1 full standby current ce1 3 v hc and ce2 v lc sa 20 20 25 10 15 f = 0 v cc = max. v in 3 v cc ?0.2v or 0.2v la 10 10 10 5 10
pdm41024 4 4/09/98 - rev. 3.3 capacitance (1) (t a = +25 c, f = 1.0 mhz) note:1. this parameter is determined by device characterization but is not production tested. ac test conditions symbol parameter max. unit c in input capacitance 8 pf c out output capacitance 8 pf input pulse levels v ss to 3.0v input rise and fall times 3 ns input timing reference levels 1.5v output reference levels 1.5v output load see figures 1 and 2 figure 1. output load equivalent figure 2. output load equivalent (for t lzce , t hzce , t lzwe , t hzwe , t lzoe , t hzoe ) +5v 480 w 255 w d out 5 pf +5v 480 w 255 w d out 30 pf figure 3. 5 4 3 2 1 0 0 30 60 90 120 typical delta t aa vs capacitive loading additional lumped capacitive loading (pf) delta t aa - ns
pdm41024 rev. 3.3 - 4/09/98 5 1 2 3 4 5 6 7 8 9 10 11 12 t rc t ace t aa t lzce t hzce t lzoe t hzoe t aoe addr ce1 ce2 oe d out data valid read cycle no. 1 (4, 5) read cycle no. 2 (2, 4, 6) ac electrical characteristics shaded area = preliminary data notes referenced are after data retention table. description -10 (7) -12 (7) -15 read cycle sym min. max. min. max. min. max. units read cycle time t rc 10 12 15 ns address access time t aa 10 12 15 ns chip enable access time t ace 10 12 15 ns output hold from address change t oh 3 33ns chip enable to output in low z (1,3) t lzce 5 55ns chip disable to output in high z (1,2,3) t hzce 667ns chip enable to power up time (3) t pu 0 00ns chip disable to power down time (3) t pd 10 12 15 ns output enable access time t aoe 666ns output enable to output in low z (1,3) t lzoe 0 00ns output disable to output in high z (1,3) t hzoe 666ns t rc
t aa
t oh
previous data valid d out addr
data valid
pdm41024 6 4/09/98 - rev. 3.3 write cycle no. 1 (write enable controlled) write cycle no. 2 (write enable controlled) t wc
t aw
t wp2
t cw
t ah
t as
t dh
t ds
t lzwe
t hzwe
addr
ce1
ce2
we
d out high-z d in data valid note: output enable (oe ) is inactive (high) t wc
t aw
t wp1
t cw
t ah
t as
t dh
t ds
addr
ce1
ce2
we
d out high-z d in data valid
pdm41024 rev. 3.3 - 4/09/98 7 1 2 3 4 5 6 7 8 9 10 11 12 write cycle no. 3 (chip enable controlled) ac electrical characteristics shaded area = preliminary data notes referenced are after data retention table description -10 (7) -12 (7) -15 write cycle sym min. max. min. max. min. max. units write cycle time t wc 10 12 15 ns chip enable active time t cw 10 10 11 ns address valid to end of write t aw 10 10 11 ns address setup time t as 0 00ns address hold from end of write t ah 0 00ns write pulse width t wp1 8 811ns write pulse width t wp2 8 812ns data setup time t ds 7 77ns data hold time t dh 0 00ns write disable to output in low z (1,3) t lzwe 0 00ns write enable to output in high z (1,3) t hzwe 777ns t wc t aw t wp1 t cw t ah t as t dh t ds addr ce1 ce2 we d out high-z d in data valid note: output enable (oe ) is inactive (high)
pdm41024 8 4/09/98 - rev. 3.3 low v cc data retention waveform data retention electrical characteristics (la version only) for jedec version notes: (for three previous electrical characteristics tables) 1. the parameter is tested with cl = 5 pf as shown in figure 2. transition is measured 200 mv from steady state voltage. 2. at any given temperature and voltage condition, t hzce is less than t lzce . 3. this parameter is sampled. 4. we is high for a read cycle. 5. the device is continuously selected. all the chip enables are held in their active state. 6. the address is valid prior to or coincident with the latest occurring chip enable. 7. vcc = 5v 5%. ordering information symbol parameter test conditions min. typ. max. unit v dr v cc for retention data 2 v i ccdr data retention current ce1 3 v cc ?0.2v or ce2 v ss + 0.2v v in 3 v cc ?0.2v or 0.2v v cc = 2v 500 m a v cc = 3v 750 m a t cdr chip deselect to data retention time 0 ns t r (3) operation recovery time t rc ns don't care v cc v
v ih il t cdr v t r 4.5v 4.5v data retention mode ce1 dr ce2 v dr 0.2v v
v ih il device type power speed package type process temp. range preferred shipping container commercial (0 to +70 c) 10 commercial only 12 15 (use 15 ns for slower designs) sa standard power la low power blank i industrial (-40 to +85 c) a automotive (-40 to +105 c) blank tubes tr tape & reel ty tray pdm41024 - 1 meg (128kx8) static ram xxxxx x xx x x x tso 32-pin 300-mil plastic soj so 32-pin 400-mil plastic soj t 32-pin plastic tsop (i)
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